近年來深度學習的發展受益於硬體技術的進步及演算法的優化，已經廣泛應用於圖形辨識、圖形及文字生成等領域，然而受物聯網及穿戴式裝置興起的影響，傳輸時間反而是運算速度受限的主因，邊緣運算的概念逐漸受到重視。因此本論文提出基於非重疊離子植入元件所形成之儲存兼計算元件，達成記憶體內運算加速研究，並以CMOS 0.25µm製程製作晶片驗證。
本研究將採用一個基於多層感知機(Multilayer perceptron, MLP)的深度神經網路架構，以彩色圖庫Cifar-10 中5萬筆訓練資料集作為網路模型訓練對象，並以1000筆測試集資料進行驗證，透過參數微調將模型參數縮至457K左右，並且依然保有驗證資料90.02%以上的辨識率。透過遷移式學習將網路模型成功於微控制器中運行，並將部分權重參數轉移至非重疊離子植入元件模型進行記憶體內運算。最終實驗結果顯示非重疊離子植入元件降低微控制器內存占用34.8%並且提高運算速度約15%，辨識率降至77.88%。
In recent years, the development of deep learning has benefited from advances in hardware technology and algorithm optimization. It has been widely applied in fields such as image recognition, image and text generation, and so on. However, due to the rise of the Internet of Things and wearable devices, transmission time has become a limiting factor for computational speed. The concept of edge computing is gradually gaining importance. Therefore, this paper proposes a storage and computation element based on non-overlapping ion implantation components to achieve research on memory-based computation acceleration. The chip is manufactured using a CMOS 0.25µm process for validation.
This study will adopt a deep neural network architecture based on a Multilayer Perceptron (MLP). It uses a dataset of 50,000 training samples from the Cifar-10 color image library as the training target for the neural network model. Validation is performed using 1,000 test dataset samples. Through parameter tuning, the model's parameters are reduced to approximately 457K, while still maintaining a recognition rate of over 90.02% on the validation data. Transfer learning is employed to successfully run the network model on a microcontroller, and some weight parameters are transferred to the non-overlapping ion implantation component model for in-memory computation. The final experimental results show that the non-overlapping ion implantation component reduces memory consumption within the microcontroller by 34.8% and increases computation speed by approximately 15%, with a recognition rate reduced to 77.88%.
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