function void uvm_reg_field::do_predict(uvm_reg_item rw, uvm_predict_e kind = UVM_PREDICT_DIRECT, uvm_reg_byte_en_t be = - 1 ); uvm_reg_data_t field_val = rw.value[ 0 ] & (( 1 << m_size)- 1 ); if (rw.status != UVM_NOT_OK) rw.status = UVM_IS_OK; // Assume that the entire field is enabled if (!be[ 0 ]) return ; m_fname = rw.fname; m_lineno = rw.lineno; case (kind) UVM_PREDICT_WRITE: begin uvm_reg_field_cb_iter cbs = new ( this ); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) field_val = XpredictX(m_mirrored, field_val, rw.map); m_written = 1 ; for (uvm_reg_cbs cb = cbs.first(); cb != null ; cb = cbs.next()) cb.post_predict( this , m_mirrored, field_val, UVM_PREDICT_WRITE, rw.path, rw.map); field_val &= ( ' b1 << m_size)-1; UVM_PREDICT_READ: begin uvm_reg_field_cb_iter cbs = new ( this ); if (rw.path == UVM_FRONTDOOR || rw.path == UVM_PREDICT) begin string acc = get_access(rw.map); if (acc == " RC " || acc == " WRC " || acc == " WSRC " || acc == " W1SRC " || acc == " W0SRC " ) field_val = 0 ; // (clear) else if (acc == " RS " || acc == " WRS " || acc == " WCRS " || acc == " W1CRS " || acc == " W0CRS " ) field_val = ( ' b1 << m_size)-1; // all 1 ' s ( set ) else if (acc == " WO " || acc == " WOC " || acc == " WOS " || acc == " WO1 " || acc == " NOACCESS " ) return ; for (uvm_reg_cbs cb = cbs.first(); cb != null ; cb = cbs.next()) cb.post_predict( this , m_mirrored, field_val, UVM_PREDICT_READ, rw.path, rw.map); field_val &= ( ' b1 << m_size)-1; UVM_PREDICT_DIRECT: begin if (m_parent.is_busy()) begin `uvm_warning( " RegModel " , { " Trying to predict value of field ' " , get_name(), " ' while register ' " ,m_parent.get_full_name(), " ' is being accessed " }) rw.status = UVM_NOT_OK; endcase // update the mirror with predicted value m_mirrored = field_val; m_desired = field_val; this .value = field_val; endfunction: do_predict