The main purpose of this thesis is to use a Field Programmable Gate Array (FPGA) and an embedded NiosII processor to develop a digital motion controller IC for XYZ table, which is driven by three PMSMs (Permanent Magnet Synchronous Motors). The motion controller IC includes two modules. The first module, which performs three PMSM’s position servo controllers for XYZ table, is implemented by hardware in FPGA. Each Intellectual Property (IP) for position servo controller includes a Self-Tuning neural-PID Controller circuit, Quadrature Encoder Pulse (QEP) capture circuits, Space Vector Pulse Width Modulation (SVPWM) circuits, current read circuit and current vector control circuit. This IP is designed by VHDL language. The second module, which performs the motion trajectory planning for XYZ table, is implemented by software in Nios II processor. The motion trajectory evaluated in this thesis includes the step response, sinusoid response, point to point motion control tracking, circle trajectory tracking, window trajectory tracking, star trajectory tracking and spiral trajectory tracking, etc. The program in Nios II processor is coded using C language. Therefore, to build up a fully digital motion controller for XYZ table, such as three current controllers for PMSM, three position/speed controllers and one trajectory planning, are all implemented by a single FPGA chip. Finally, an experimental system constructed by an FPGA experimental board, one peripheral circuit ( two QEP circuirs for linear encoder, four A/D converters, six limit switch circuits), three inverters and one XYZ table is set up to demonstrate the correctness and effectiveness of the proposed motion control IC of XYZ table.
摘要 i
英文摘要 ii
目次 iii
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究背景與目的 1
1.2 文獻回顧 3
1.3 本文架構 4
第二章 永磁同步馬達介紹及自調式類神經PID設計 6
2.1簡介 6
2.2永磁同步馬達數學模式 7
2.3 座標轉換 9
2.4 空間向量脈波寬度調變(SVPWM) 11
2.4.1 SVPWM 11
2.4.2 SVPWM計算程序 12
2.5 電流迴路於FPGA晶片實現之架構 14
2.6 自調式類神經PID簡介 15
2.7 自調式類神經PID架構 16
2.7.1 PID控制器 17
2.7.2參考模型(Reference model) 18
2.7.3徑向基底函數類神經網路(RBFNN) 19
2.7.3.1徑向基底函數類神經網路架構 19
2.7.3.2徑向基底函數類神經網路學習演算法 21
2.7.4自調式類神經PID之參數調整 22
2.7.5自調式類神經PID計算程序 24
第三章 單軸平台控制器之硬體實現 25
3.1簡介 25
3.2電流控制器之電路設計 26
3.2.1座標轉換電路 22
3.2.1.1正餘弦產生電路 27
3.2.1.2兩軸旋轉座標至兩軸靜止座標轉換電路 28
3.2.1.3兩軸靜止座標至靜止三軸座標轉換電路 28
3.2.1.4靜止三相座標至兩軸靜止座標轉換電路 29
3.2.1.5兩軸靜止座標至兩軸旋轉座標轉換電路 30
3.2.1.6比例積分(PI)控制器電路 30
3.2.2利用有限狀態機設計座標轉換電路與PI控制器電路 30
3.2.3方型波編碼器脈波電路 33
3.2.4空間向量脈波寬度調變(SVPWM)電路 35
3.2.5類比/數位轉換電路 38
3.3 位置速度控制器之電路設計 39
3.3.1參考模型電路設計 40
3.3.2 PID控制器電路設計 40
3.3.3徑向基底函數類神經網路電路設計 43
3.3.3.1徑向基底函數類神經網路輸出電路設計 44
3.3.3.1.1歐式距離產生電路 45
3.3.3.1.2指數產生電路 47
3.3.3.2徑向基底函數類神經網路參數調整學習電路設計 48
3.3.3.3 Jacobian電路設計 49
3.3.4參考模型電路設計 50
第四章 XYZ平台運動控制晶片設計與模擬 52
4.1簡介 52
4.2電流控制器之電路設計 54
4.3 NiosII設計與應用 55
4.3.1 NiosII程式設計 55
4.3.2軌跡規劃 58
4.3.2.1長行程點對點軌跡規劃 58
4.3.2.2圓形軌跡 60
4.3.2.3星形軌跡 61
4.3.2.4窗形軌跡 63
4.3.2.5螺旋形軌跡 64
4.4 XYZ平台運動控制晶片驗證與模擬 65
4.4.1指數產生電路 65
4.4.2自調式類神經PID電路模擬 69
第五章 實驗架構與實驗結果 72
5.1簡介 72
5.2實驗系統架構 73
5.3 XYZ平台之單軸響應分析 75
5.3.1位置迴路使用PID控制器 76
5.3.2位置迴路使用自調式類神經PID控制器 81
5.4單軸運動軌跡使用梯形軌跡規劃 87
5.5 XYZ平台雙軸運動控制 91
5.5.1 XYZ平台雙軸運動控制使用PID控制器 92
5.5.2 XYZ平台雙軸運動控制使用自調式類神經PID控制器 95
5.5.3 XYZ平台雙軸雙軌跡追蹤性能分析 98
5.6 XYZ平台三軸運動控制 100
5.6.1 XYZ平台三軸運動控制使用PID控制器 100
5.6.2 XYZ平台雙軸運動控制使用自調式類神經PID控制器 102
第六章 結論與未來研究方向 105
6.1結論 105
6.2未來研究方向 106
參考文獻 107
作者簡介 112
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