input clk ,///25M系统时钟 input rst_n , input [47:0] s_adc_cfg_data_ascii ,//输入6个ascii码 output [23:0] s_adc_cfg_data_hex //输出6个HEX数据 reg [3:0] o_adc_cfg_data_hex_6 ; reg [3:0] o_adc_cfg_data_hex_5 ; reg [3:0] o_adc_cfg_data_hex_4 ; reg [3:0] o_adc_cfg_data_hex_3 ; reg [3:0] o_adc_cfg_data_hex_2 ; reg [3:0] o_adc_cfg_data_hex_1 ; always @(*) begin //-----------------------------ascii转hex 解析----------------------------------------- ascii2binary(s_adc_cfg_data_ascii[47:40] ,o_adc_cfg_data_hex_6 ) ; ascii2binary(s_adc_cfg_data_ascii[39:32] ,o_adc_cfg_data_hex_5 ) ; ascii2binary(s_adc_cfg_data_ascii[31:24] ,o_adc_cfg_data_hex_4 ) ; ascii2binary(s_adc_cfg_data_ascii[23:16] ,o_adc_cfg_data_hex_3 ) ; ascii2binary(s_adc_cfg_data_ascii[15:8] ,o_adc_cfg_data_hex_2 ) ; ascii2binary(s_adc_cfg_data_ascii[7:0] ,o_adc_cfg_data_hex_1 ) ; assign s_adc_cfg_data_hex = {o_adc_cfg_data_hex_6,o_adc_cfg_data_hex_5,o_adc_cfg_data_hex_4,o_adc_cfg_data_hex_3,o_adc_cfg_data_hex_2,o_adc_cfg_data_hex_1} ; task ascii2binary; input [7:0] ascii_in; output [3:0]out; begin case (ascii_in) 8'h30: out = 4'd0; //ASCII value 48 = 0 in Binary 8'h31: out = 4'd1; //ASCII value 49 = 1 in Binary 8'h32: out = 4'd2; //ASCII value 50 = 2 in Binary 8'h33: out = 4'd3; //ASCII value 51 = 3 in Binary 8'h34: out = 4'd4; //ASCII value 52 = 4 in Binary 8'h35: out = 4'd5; //ASCII value 53 = 5 in Binary 8'h36: out = 4'd6; //ASCII value 54 = 6 in Binary 8'h37: out = 4'd7; //ASCII value 55 = 7 in Binary 8'h38: out = 4'd8; //ASCII value 56 = 8 in Binary 8'h39: out = 4'd9; //ASCII value 57 = 9 in Binary 8'h61: out = 4'd10; //ASCII value 97 = a in Binary 8'h62: out = 4'd11; //ASCII value 98 = b in Binary 8'h63: out = 4'd12; //ASCII value 99 = c in Binary 8'h64: out = 4'd13; //ASCII value 100 = d in Binary 8'h65: out = 4'd14; //ASCII value 101 = e in Binary 8'h66: out = 4'd15; //ASCII value 102 = f in Binary default: out = 4'd0; endcase endtask endmodule 编译指令是以 ` 为前缀， ASCII 为0x60，而不是单引号 ’ ，单引号的 ASCII 为0x27 编译指令从处理它的位置就一直保持有效，除非后面被自己或者其他编译指令覆盖或者取消掉 `celldefine 和 `endcelldefine `celldefine 和 `endcelldefine 用于将模块标记为单元（cell），一般在标准单元库中使用，一般来说写的代 码 都是模块，很少去把它标记为单元 最好在模块外面使用这两条指令 `celldefine