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Abstract

In this paper, we explore the potential of improving AES-based schemes by integrating SHA instructions alongside AES instructions, starting from the key observation that SHA instructions can be executed in parallel with AES instructions on modern processors. We investigate conditions for parallel execution, the invocation ratio, and overhead of type conversions, and then provide guidelines for efficient SHA instruction usage with AES instructions. Applying these guidelines, we integrate SHA round functions into the AES-based short-input hash functions of Simpira and Areion, resulting in approximately 50% faster performance by achieving security with fewer iterations. Besides, we apply integration of SHA instructions to AES-based AEAD schemes of AEGIS-128L, which supports a 256-bit tag but has recently been shown to fall short of providing full 256-bit forgery security. We demonstrate that hybrid schemes can achieve 256-bit forgery security for AEGIS-128L while preserving performance.

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Takuro Shiraya, Subhadeep Banik, Tatsuya Ishikawa, Ryoma Ito, Mostafizar Rahman, Kosei Sakamoto, Atsushi Tanaka, Shion Utsumi, and Takanori Isobe, Exploring SHA Instructions and Its Application to AES-based Schemes. IACR Communications in Cryptology , vol. 2, no. 3, Oct 06, 2025, doi: 10.62056/anxrudy6b. BibTeX, etc

@article{10.62056/anxrudy6b,
         author={Takuro Shiraya and Subhadeep Banik and Tatsuya Ishikawa and Ryoma Ito and Mostafizar Rahman and Kosei Sakamoto and Atsushi Tanaka and Shion Utsumi and Takanori Isobe},
         title={Exploring {SHA} Instructions and Its Application to {AES}-based Schemes},
         volume={2},
         number={3},
         year={2025},
         date={2025-10-06},
         issn={3006-5496},
         doi={10.62056/anxrudy6b},
         journal={{IACR} Communications in Cryptology},
         publisher={International Association for Cryptologic Research}
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TY  - JOUR
AU  - Takuro Shiraya
AU  - Subhadeep Banik
AU  - Tatsuya Ishikawa
AU  - Ryoma Ito
AU  - Mostafizar Rahman
AU  - Kosei Sakamoto
AU  - Atsushi Tanaka
AU  - Shion Utsumi
AU  - Takanori Isobe
PY  - 2025
TI  - Exploring SHA Instructions and Its Application to AES-based Schemes
JF  - IACR Communications in Cryptology
JA  - CIC
VL  - 2
IS  - 3
DO  - 10.62056/anxrudy6b
UR  - https://doi.org/10.62056/anxrudy6b
AB  - <p>In this paper, we explore the potential of improving AES-based schemes by integrating SHA instructions alongside AES instructions, starting from the key observation that SHA instructions can be executed in parallel with AES instructions on modern processors. We investigate conditions for parallel execution, the invocation ratio, and overhead of type conversions, and then provide guidelines for efficient SHA instruction usage with AES instructions. Applying these guidelines, we integrate SHA round functions into the AES-based short-input hash functions of Simpira and Areion, resulting in approximately 50% faster performance by achieving security with fewer iterations. Besides, we apply integration of SHA instructions to AES-based AEAD schemes of AEGIS-128L,  which supports a 256-bit tag but has recently been shown to fall short of providing full 256-bit forgery security. We demonstrate that hybrid schemes can achieve 256-bit forgery security for AEGIS-128L while preserving performance. </p>
ER  -
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Takuro Shiraya, Subhadeep Banik, Tatsuya Ishikawa, Ryoma Ito, Mostafizar Rahman, Kosei Sakamoto, Atsushi Tanaka, Shion Utsumi, and 
Takanori Isobe, Exploring SHA Instructions and Its Application to AES-based Schemes. IACR Communications in Cryptology, vol. 2, no. 3, Oct 06, 2025, doi: 10.62056/anxrudy6b.
            Copy to clipboard
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