本文介绍了一种基于混合信号的新型可配置环形振荡器 (CRO) 物理不可克隆功能 (PUF) 架构，适用于资源受限的物联网 (IoT) 设备。PUF 可以通过从制造变化中获得的独特继承指纹来保护物联网设备。然而，传统的环形振荡器 (RO) PUF 需要 RO 的多个副本来生成大量挑战响应对 (CRP)，这使其在物联网环境中的使用无效。使用本手稿中提出的可重构异质材料异质电介质 FET（HM-HD-RFET）的概念，我们设计了一种新颖的 CRO，它允许 512 个挑战和一个 sigma delta 模数转换器（ADC）在末端生成一个流响应位。HM-HD-RFET 可以通过两个极性门 (PG) 配置为四种不同的晶体管组合，并且可以使用控制门 (CG) 控制它们的开关。接下来，我们将 HM-HD-RFET 与可配置硅 FET (Si-RFET) 和同质电介质 FET (HM-RFET) 进行比较，以表明所提出的器件在所有四种配置中都表现良好，双极性可忽略不计。器件特性在 Silvaco Atlas 工具中实现，电路实现在 Cadence 中使用基于 Verilog-A 的查找表方法完成，CRO PUF 的属性在 MATLAB 中计算。我们将 HM-HD-RFET 与可配置硅 FET (Si-RFET) 和同质电介质 FET (HM-RFET) 进行比较，以表明所提出的器件在所有四种配置中都表现良好，双极性可忽略不计。器件特性在 Silvaco Atlas 工具中实现，电路实现在 Cadence 中使用基于 Verilog-A 的查找表方法完成，CRO PUF 的属性在 MATLAB 中计算。我们将 HM-HD-RFET 与可配置硅 FET (Si-RFET) 和同质电介质 FET (HM-RFET) 进行比较，以表明所提出的器件在所有四种配置中都表现良好，双极性可忽略不计。器件特性在 Silvaco Atlas 工具中实现，电路实现在 Cadence 中使用基于 Verilog-A 的查找表方法完成，CRO PUF 的属性在 MATLAB 中计算。
This article presents a mixed signal-based novel configurable ring oscillator (CRO) physical unclonable function (PUF) architecture for resource constrained Internet of Things (IoT) devices. PUF can protect the IoT devices through their unique inherited fingerprints obtained from the manufacture variations. However, the conventional ring oscillator (RO) PUF need multiple replicas of ROs to produce a large set of challenge response pairs (CRPs) which invalidates its usage in an IoT environment. Using the concept of reconfigurable hetero material hetero dielectric FET (HM-HD-RFET) proposed in this manuscript, we have designed a novel CRO which allows 512 challenges and a sigma delta analog to digital converter (ADC) at the end generates a stream of response bits. HM-HD-RFET can be configured into four different combinations of transistors through two polarity gates (PGs) and their switching can be controlled using a control gate (CG). Next, we compare HM-HD-RFET with configurable silicon FET (Si-RFET) and homogenous dielectric FET (HM-RFET) to show that the proposed device performs well in all of the four configurations with negligible ambipolarity. The device characteristics is realized in Silvaco Atlas tool, circuit implementation is done in Cadence using Verilog-A based look table approach and properties of CRO PUF are computed in MATLAB.
